The present invention relates to the field of integrated circuits that include capacitor arrays, particularly for use in switched-capacitor amplifiers, digital-to-analog converters and analog-to-digital converters.
Arrays of precision capacitors are used in various switched capacitor circuits. One example is illustrated in FIG. 1, where a switched-capacitor DAC using (n+1) capacitors (C, 2C, . . . , 2n−1C, 2nC) with a common top plate and separate bottom plates is shown. The use of a similar capacitor array of capacitors (C1=C, C2=2C, . . . , CK+1=2K−1C) in an ADC is presented in FIG. 2. In both cases, the values of the capacitances are powers of 2 of a unit capacitance. For matching reasons, the capacitor arrays are built from unit capacitors, interconnected as to provide the appropriate values, and distributed in the array as to compensate for the gradients of the dielectric thickness. In the particular cases shown in FIGS. 1 and 2, the top plates of the capacitors of the arrays are common.
The conventional arrays of precision capacitors are usually built using polysilicon-polysilicon structures. The ratio of the capacitances is usually of great importance, and in order to compensate for the thickness gradients in the dielectric layer(s), the capacitors are built using unit cells arranged in a common centroid array. This strategy is illustrated in FIG. 3b, for a 3-bit ADC built using the schematic of FIG. 3a. The capacitors marked 2, 4, 8 are, respectively, belonging to the capacitors C2=2*C, C4=4*C, C8=8*C. The capacitors with a similar marking are connected in parallel. Because in this array structure the top plate is common, only the bottom plates of the similarly marked capacitors are connected together through dedicated lines. One can also see capacitors marked D (dummy), which have no active role in the array. Their presence enhances the matching of the capacitors in the array, by providing similar surroundings to each unit capacitor.
In a digital process, usually there is only one layer of polysilicon available and the precision capacitors are implemented as a sandwiched structure of three metal layers, as shown in FIG. 4. The internal layer 14 is the top plate, while the external layers 16 and 18 are connected together and form the bottom plate of the capacitor. Usually, the connection 17 between the layers forming the bottom plate is made at the periphery of each capacitor.
When the capacitors are arranged in an array with a common top plate, there is a need to connect the various bottom plates in order to form the required capacitor configurations. In a polysilicon-polysilicon capacitor array, the connection between the bottom plates is usually made in one or more of the metal layers, on top of the capacitor structures. For a metal-metal capacitor, the connection is usually made in an extra layer of metal.
When using a metal-metal sandwich structure, the specific capacitance is small and the capacitors occupy a large area of the integrated circuit. Besides the greater level of noise induced into the substrate or collected from the substrate by a big capacitor array, a large percentage of the area is occupied by the connection between the various existing bottom plate layers, thus reducing the useful area allocated to the capacitors and making the layout more difficult.